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(R)
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
DESCRIPTION:
IDT54/74FCT299 IDT54/74FCT299A IDT54/74FCT299C
Integrated Device Technology, Inc.
FEATURES:
* * * * * * * * * * * * * * IDT54/74FCT299 equivalent to FASTTM speed IDT54/74FCT299A 25% faster than FAST IDT54/74FCT299C 35% faster than FAST Equivalent to FAST output drive over full temperature and voltage supply extremes IOL = 48mA (commercial) and 32mA (military) CMOS power levels (1mW typ. static) TTL input and output level compatible CMOS output level compatible Substantially lower input current levels than FAST (5A max.) 8-input universal shift register JEDEC standard pinout for DIP and LCC Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B Standard Military Drawing# 5962-86862 is listed on this function. Refer to section 2.
The IDT54/74FCT299 and IDT54/74FCT299A/C are built using an advanced dual metal CMOS technology. The IDT54/ 74FCT299 and IDT54/74FCT299A/C are 8-input universal shift/storage registers with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
FUNCTIONAL BLOCK DIAGRAM
S1 S0
DS7 DS0
CP CD Q0 MR OE1 OE2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
2561 drw 01
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q
CD
D CP Q Q7
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1994 Integrated Device Technology, Inc.
MAY 1992
DSC-4604/3
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IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND
1 2 3 4 5 6 7 8 9 10
20 19
P20-1 D20-1 S020-2 & E20-1
18 17 16 15 14 13 12 11
Vcc S1 DS7 Q7 I/O7 I/O5 I/O 3 I/O1 CP DS0
I/O6 I/O4 I/O2 I/O0 Q0
OE2 OE 1 S0 Vcc S1
32 4 5 6 7 8 1 20 19 18 17 16 15 14 9 10 11 12 13
PIN CONFIGURATIONS
L20-2
DS7 Q7 I/O7 I/O5 I/O3
DIP/SOIC/CERPACK TOP VIEW
MR GND DS0 CP I/O 1
LCC TOP VIEW
2561 drw 02
PIN DESCRIPTION
Pin Names CP DS0 DS7 S0, S1 Description Clock Pulse Input (Active Edge Rising) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW) 3-State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3-State Parallel Outputs Serial Outputs
2561 tbl 01
FUNCTION TABLE(1)
Inputs
MR S1
L H H H H X H L H L
S0 X H H L L
CP X X
Response Asynchronous Reset Q0-Q7 = LOW Parallel Load; I/On Qn Shift Right; DS0 Q0, Q0 Q1, etc. Shift Left; DS7 Q7, Q7 Q6, etc. Hold
2561 tbl 02
MR OE1, OE2
I/O0-I/O7 Q0, Q7
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating (2) Terminal Voltage VTERM with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation DC Output Current IOUT Commercial Military Unit -0.5 to +7.0 -0.5 to +7.0 V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Typ. Max. Unit 6 8 10 12 pF pF
-0.5 to VCC
-0.5 to VCC
V
NOTE: 2561 tbl 04 1. This parameter is guaranteed by characterization data and not tested.
0 to +70 -55 to +125 -55 to +125 0.5 120
-55 to +125 -65 to +135 -65 to +150 0.5 120
C C C W mA
NOTES: 2561 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5 unless otherwise noted. 2. Inputs and VCC terminals only. 3. Outputs and I/O terminals only.
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IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IIH IIL VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Except I/O Pins) Input LOW Current (Except I/O Pins) Input HIGH Current (I/O Pins Only) Input LOW Current (I/O Pins Only) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage Vcc = Min., IN = -18mA Vcc = Max.(3), VO = GND Vcc = 3V, VIN = VLC or VHC, IOH = -32A Vcc = Min. VIN = VIH or VIL VOL Output LOW Voltage IOH = -300A IOH = -12mA MIL. IOH = -15mA COM'L. Vcc = 3V, VIN = VLC or VHC, IOL = 300A Vcc = Min. VIN = VIH or VIL IOL = 300A IOL = 32mA MIL. IOL = 48mA COM'L. VCC = Max. Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND VI = VCC VI = 2.7V VI = 0.5V VI = GND Min. 2.0 -- -- -- -- -- -- -- -- -- -- -60 VHC VHC 2.4 2.4 -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 Max. -- 0.8 5 5(4) -5(4) -5 15 15(4) -15(4) -15 -1.2 -- -- -- -- -- VLC VLC(4) 0.5 0.5
2561 tbl 05
Unit V V A
A
V mA V
V
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested.
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IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) Vcc = Max. VIN VHC; VIN VLC Vcc = Max. VIN = 3.4V(3) Vcc = Max. Outputs Open OE1 = OE2 = GND MR = VCC S0 = S1 = VCC DS0 = DS1 = GND One Input Toggling 50% Duty Cycle Vcc = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE1 = OE2 = GND MR = VCC S0 = S1 = VCC DS0 = DS7 = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle Vcc = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE1 = OE2 = GND MR = VCC S0 = S1 = VCC DS0 = DS7 = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle VIN VHC VIN VLC Min. -- -- -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2.0 0.25 Unit mA mA mA/MHz
IC
Total Power Supply Current(6)
VIN VHC VIN VLC (FCT)
--
1.7
4.0
mA
VIN = 3.4V VIN = GND
--
2.2
6.0
VIN VHC VIN VLC (FCT)
--
4.0
7.8(5)
VIN = 3.4V VIN = GND
--
6.2
16.8(5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2561 tbl 06
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IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299 Com'l. Symbol Parameter Propagation Delay tPLH tPHL CP to Q0 or Q7 tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay CP to I/On Propagation Delay MR to Q0 or Q7 Propagation Delay MR to I/On Output Enable Time OEn to I/On Output Disable Time OEn to I/On Set-up Time HIGH or LOW S0 or S1 to CP Hold Time HIGH or LOW S0 or S1 to CP Set-up Time HIGH or LOW I/On, DS0 or DS7 to CP Hold Time HIGH or LOW I/On, DS0 or DS7 to CP CP Pulse width HIGH or LOW Mil. IDT54/74FCT299A Com'l. Mil. IDT54/74FCT299C Com'l. Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit CL = 50pF 2.0 10.0 2.0 14.0 2.0 7.2 2.0 9.5 2.0 6.5 2.0 7.5 ns RL = 500 2.0 2.0 2.0 1.5 1.5 7.5 12.0 10.0 15.0 11.0 7.0 -- 2.0 2.0 2.0 1.5 1.5 7.5 12.0 10.5 15.0 15.0 9.0 -- 2.0 2.0 2.0 1.5 1.5 3.5 7.2 7.2 8.7 6.5 6.0 -- 2.0 2.0 2.0 1.5 1.5 4.0 9.5 9.5 11.5 7.5 6.5 -- 2.0 2.0 2.0 1.5 1.5 3.5 6.5 6.5 6.5 6.5 6.0 -- 2.0 2.0 2.0 1.5 1.5 4.0 7.5 7.5 7.5 7.5 6.5 -- ns ns ns ns ns ns
tH
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
1.0
--
ns
tSU
5.5
--
5.5
--
4.0
--
4.5
--
4.0
--
4.5
--
ns
tH
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
tW tW tREM
7.0 7.0 7.0
-- -- --
7.0 7.0 7.0
-- -- --
5.0 5.0 5.0
-- -- --
6.0 6.0 6.0
-- -- --
5.0 5.0 5.0
-- -- --
6.0 6.0 6.0
-- -- --
ns ns ns
2561 tbl 07
MR Pulse Width
LOW Recovery Time MR to CP
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
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IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 V OUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: 2561 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t REM 3V 1.5V 0V 3V 1.5V 0V tH 3V 1.5V 0V 3V 1.5V 0V
PULSE WIDTH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
t SU
tH
PROPAGATION DELAY
3V 1.5V tPLH OUTPUT t PLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V t PHL 0V VOH 1.5V VOL
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT t PZL OUTPUT NORMALLY SWITCH LOW CLOSED t PZH OUTPUT SWITCH NORMALLY OPEN HIGH 3.5V 1.5V 0.3V t PHZ 0.3V 1.5V 0V V OH 0V t PLZ DISABLE 3V 1.5V 0V 3.5V V OL
SAME PHASE INPUT TRANSITION
NOTES 2561 drw 04 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT299/A/C FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX Temperature Range FCT X Device Type X Package X Process
Blank B P D SO L E 299 299A 299C 54 74
Commercial MIL-STD-883, Class B Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK 8-Input Universal Shift Register Fast 8-Input Universal Shift Register Super Fast 8-Input Universal Shift Register -55C to +125C 0C to +70C
2561 drw 03
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